1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same. Particularly, the present invention relates to a semiconductor device which has both NAND-type and NOR-type cell transistors as memory cell transistors (hereinafter, referred to as cell transistors) simultaneously present on a single semiconductor substrate, and to a method for producing the same.
2. Description of the Related Art
Conventionally known types of memory cells in a mask ROM are a NAND-type ROM and a NOR-type ROM. The NAND-type ROM has a plurality of columns of transistors, each column being made of a plurality of cell transistors connected in series. In each of the transistor columns, enhancement-type transistors and depletion-type transistors are arranged in accordance with ROM data so that the ROM data can be written.
The NOR-type ROM has a plurality of columns of transistors, each including a plurality of cell transistors connected in parallel with respect to the bit line. In each of the transistor columns, threshold voltages are set above the power source voltage for the transistors selected in accordance with the ROM data so that the ROM data can be written.
In general, NAND-type ROMs are excellent in high integration but poor in high speed operation. Conversely, NOR-type ROMs are excellent in high speed operation but poor in high integration. The reason why the NOR-type ROMs are poor in high integration is as follows. The NOR-type ROM generally requires one contact hole for wire connection for every two cell transistors. This makes it necessary to reserve both a region for contact hole formation and a margin for mask alignment during contact hole formation. Consequently, miniaturization of memory cells becomes difficult.
As a result, NAND-type ROMs have mainly been used for the realization of high integration. The reason for this is that since a plurality of cell transistors are connected in series to configure a plurality of transistor columns, the contact holes need only to be formed at both ends of the transistor columns. The larger the number of transistors to be connected in series, the higher the integration becomes.
However, there still is a growing need for higher integration of memory cells. In order to further pursue high integration using the NAND-type ROMs, it is necessary to reduce displacement of isolation walls.
One conventional example which is to meet such demand is a high integration NOR-type ROM (hereinafter referred to as the first conventional example) in which device isolation is achieved without forming an isolation wall, thereby reducing the step of the isolation wall, and the contact hole for wire connection is not formed for every memory cell. Therefore, advantages of both the NAND-type ROM and the NOR-type ROM are retained.
The high integration NOR-type ROM of the first conventional example will be described a bit further with reference to FIGS. 54A, 54B, 54C and 54D. A plurality of high concentration diffusion layers 202 and 203 which become source/drain regions and bit lines are formed in parallel in a memory cell formation region of a semiconductor substrate 201. Provided over this semiconductor substrate 201 with a gate insulating film 204 inserted therebetween are a plurality of gate electrodes (word lines) 205 which extend perpendicular to the high concentration diffusion layers 202 and 203 which become bit lines. Regions where the gate electrodes 205 or the high concentration diffusion layers 202 and 203 are not formed are ion-implanted with an impurity having conductivity type different from that of the source/drain regions 202. These regions 206 are designated by function as an isolation between the cell transistors. In FIG. 54A, reference numerals 251 and 252 indicate the cell transistor region.
Since memory cells having such a configuration do not have the isolation wall such as a LOCOS (local oxidation of silicon) film, the semiconductor substrate 201 has a planar surf ace. For this reason, the gate electrodes 205 can be disposed with a pitch which is less than the typical fabrication limit. Furthermore, since the isolation walls 206 can be self-aligningly ion-implanted using the gate electrodes 205 as a mask, high integration of the memory cells is greatly facilitated.
However, even a high integration NOR-type ROM described above has problems to be overcome in order to further achieve higher integration as the above-described conventional NAND-type ROM does. Methods for further achieving higher integration in NAND-type ROMs or NOR-type ROM described above include a method where the gate electrodes have a multi-layer structure and a method where the isolation wall is not provided.
An example of the former is disclosed in Japanese Laid-Open Patent Publication No. 53-41188 (hereinafter, referred to as the second conventional example) and an example of the latter is disclosed in Japanese Laid-Open Patent Publication No. 63-131568 (hereinafter, referred to as the third conventional example).
FIGS. 55A, 55B and 55C illustrate the conventional example suggested in Japanese Laid-Open Patent Publication No. 53-41188. This conventional example was applied to a NAND-type ROM. As illustrated in the figures, a first gate oxide film 304 is formed on a semiconductor substrate 301, and then a plurality of first gate electrodes 305 are provided thereon in the horizontal direction with a separation of prescribed distance, thereby forming first MIS (metal insulator semiconductor)-type transistors. Furthermore, after forming the first gate electrodes 305, a second gate oxide film 306 is formed on the entire surface of the semiconductor substrate 301 so as to cover the first gate electrodes 305. Then, second gate electrodes 307 are provided thereon, thereby forming second MIS-type transistors. In this semiconductor device, the second gate electrodes 307 are provided between the first gate electrodes 305. Therefore, the occupied area for each cell transistor when viewed from above can be made one half of that in the above first conventional example. As a result, the degree of integration can be doubled.
FIGS. 56A, 56B and 56C illustrate the conventional example suggested in Japanese Laid-Open Patent Publication No. 63-131568. This conventional example was applied to a NOR-type ROM. The source regions 402 and the drain regions 403 are formed on the semiconductor substrate 401 in parallel with a separation of a channel length, and then the gate electrodes 405 are formed so as to become perpendicular to the source regions 402, the drain regions 403 and the channel regions 404 formed between the source regions 402 and the channel regions 404. These gate electrodes are also provided in a plurality of numbers in the horizontal direction with a separation of a prescribed distance. Reference numeral 406 designates a gate insulating film. According to this conventional example, since isolation walls are not present between the gate electrodes 405, a pitch between lines can be reduced thereby and higher integration of memory cells can be achieved.
However, in either of the above-described second conventional example and the third conventional example, there is a certain limit in meeting the recent demand for higher integration. Particularly, in the second conventional example, since the step between one layer and another layer becomes large, it is likely that a layer formed on these layers is torn. This complicates the production method and poses some problems when improving production efficiency.